1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of fabrication of capacitors in semiconductor wafers.
2. Background Art
Various types of capacitors, such as composite capacitors comprising several interconnected capacitors, are used in circuits in semiconductor devices, such as mixers and amplifiers, and are required to provide high capacitance density without consuming a large area on a semiconductor die (also referred to simply as a “die”). A composite capacitor can include multiple stacked layers, where each layer of the capacitor can reside in a different metal layer of a die and be electrically connected to other capacitor layers by vias. During a typical design cycle, a circuit layout design including a capacitor, such as a composite capacitor, can be verified by fabricating the circuit including the capacitor in a small-scale engineering or pilot foundry. After the layout design has been verified, the circuit including the capacitor can be mass produced in a production foundry to reduce manufacturing cost.
However, for a variety of reasons, the process parameters utilized to fabricate a capacitor in one foundry may not match the process parameters utilized to fabricate the capacitor in another foundry, thereby causing the capacitor to have a different capacitance value in each foundry. For example, a process parameter, such as a dielectric constant value of a dielectric material, can be higher in a production foundry as compared with the dielectric constant in a small-scale engineering foundry. As a result, the capacitance value of the capacitor needs to be adjusted in the production foundry to match the capacitance value of the capacitor in the small-scale engineering foundry.
In a conventional approach, the layout of the capacitor can be manually redesigned to cause the capacitance value of the capacitor in the production foundry to match the capacitance value of the capacitor in the small-scale engineering foundry. However, manually redesigning the layout of the capacitor can undesirably increase manufacturing cost and requires the data files, such as such as Graphic Data System (GDS) data files including the layout of the capacitor, to be regenerated for “tape-out” to the production foundry. Moreover, according to conventional approaches, redesigning the capacitor layout usually causes an undesirable change in the die area consumed by the capacitor.